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Ders Tanımı

Ders Kodu Yarıyıl T+U Saat Kredi AKTS
ADVANCED DIGITAL SYSTEM DESIGN AND SYNTHESIS BSM 439 7 3 + 0 3 5
Ön Koşul Dersleri
Önerilen Seçmeli Dersler
Dersin Dili Türkçe
Dersin Seviyesi Lisans
Dersin Türü SECMELI
Dersin Koordinatörü Prof.Dr. AHMET ÖZMEN
Dersi Verenler
Dersin Yardımcıları
Dersin Kategorisi
Dersin Amacı
Computer and software have been widely used for designing, verification and synthesis of complex digital systems. For each stage of this process, there are advanced technological hardware and software elements in the market. Teaching details of design, verification and synthesis stages are main goal of the course using a hardware programming language.

is aimed that Inthis course
Dersin İçeriği
Verilog-HDL is taught throughout a simple CPU design. Verification is very important at design of complex systems. Every component must be verified before integrated to the main unit. After verification, designs are synthesized to various FPGA chips which are obtained from the market.
Dersin Öğrenme Çıktıları Öğretim Yöntemleri Ölçme Yöntemleri
1 - Chooses a model as a solution for complex digital circuit problems 1 - A -
2 - Designs combinatorial logical circuit using Verilog-HDL 1 - 4 - A - C -
3 - Designs dequential logical circuit using Verilog-HDL 1 - 4 - A - C -
4 - Verifies solutions which are desinged with HDL 1 - 9 - A -
5 - Synthesizes solutions on various hardware which are designed and verified by using HDL 1 - 4 - A - C -
6 - Designs a simple CPU 1 - 4 - A -
Öğretim Yöntemleri: 1:Lecture 4:Drilland Practice 9:Simulation
Ölçme Yöntemleri: A:Testing C:Homework

Ders Akışı

Hafta Konular ÖnHazırlık
1 Introduction to digital design and hardware programming languages
2 Verilog-HDL programming language
3 Hierarchical modelling concept
4 Gate level programming model
5 Data flow programming model
6 Behavioral programming model
7 ALU design and verification
8 Register design and verification
9 Single-cycle data path design with hierarchical model
10 Single-cycle data path design verification
11 Control logic design and verification
12 Timing and delays
13 Synthesis of verified design
14 Examples of synthesis process

Kaynaklar

Ders Notu 1. Verilog HDL, A guide to Digital Designand Synthesis, Samir Palnitkar, SunSoft Press 1996.
Ders Kaynakları 1. Computer Organization and Design, The Hardware and Software Interface, D.A.Patterson, Morgan Kaufmann.
2. Computer Architecture, Single and Parallel Systems, M. Zargham, Prentice Hall.
3. Computer System Architecture, M.Mano, Prentice Hall.

Döküman Paylaşımı


Dersin Program Çıktılarına Katkısı

No Program Öğrenme Çıktıları KatkıDüzeyi
1 2 3 4 5
1 To have sufficient foundations on engineering subjects such as science and discrete mathematics, probability/statistics; an ability to use theoretical and applied knowledge of these subjects together for engineering solutions,
2 An ability to determine, describe, formulate and solve engineering problems; for this purpose, an ability to select and apply proper analytic and modeling methods,al background in describing, formulating, modeling and analyzing the engineering problem, with a consideration for appropriate analytical solutions in all necessary situations X
3 An ability to select and use modern techniques and tools for engineering applications; an ability to use information technologies efficiently, X
4 An ability to analyze a system, a component or a process and design a system under real limits to meet desired needs; in this direction, an ability to apply modern design methods, X
5 An ability to design, conduct experiment, collect data, analyze and comment on the results and consciousness of becoming a volunteer on research, X
6 Understanding, awareness of administration, control, development and security/reliability issues about information technologies, X
7 An ability to work efficiently in multidisciplinary teams, self confidence to take responsibility,
8 An ability to present himself/herself or a problem with oral/written techniques and have efficient communication skills; know at least one extra language,
9 An awareness about importance of lifelong learning; an ability to update his/her knowledge continuously by means of following advances in science and technology,
10 Understanding, practicing of professional and ethical responsibilities, an ability to disseminate this responsibility on society,
11 An understanding of project management, workplace applications, health issues of laborers, environment and job safety; an awareness about legal consequences of engineering applications,
12 An understanding universal and local effects of engineering solutions; awareness of entrepreneurial and innovation and to have knowledge about contemporary problems.

Değerlendirme Sistemi

YARIYIL İÇİ ÇALIŞMALARI SIRA KATKI YÜZDESİ
AraSinav 1 50
Odev 1 10
ProjeTasarim 1 20
ProjeTasarim 2 20
Toplam 100
Yıliçinin Başarıya Oranı 50
Finalin Başarıya Oranı 50
Toplam 100

AKTS - İş Yükü

Etkinlik Sayısı Süresi(Saat) Toplam İş yükü(Saat)
Course Duration (Including the exam week: 16x Total course hours) 16 3 48
Hours for off-the-classroom study (Pre-study, practice) 16 2 32
Mid-terms 1 8 8
Assignment 1 5 5
Project / Design 2 7 14
Final examination 1 15 15
Toplam İş Yükü 122
Toplam İş Yükü /25(s) 4.88
Dersin AKTS Kredisi 4.88
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